The present disclosure relates to an erase method for non-volatile semiconductor memory devices. More particularly, the disclosure relates to an erase method for NOR flash memory devices.
NOR flash memory is a well known type of non-volatile memory capable of retaining stored data in the absence of applied power, yet also capable of being electrically erasable and electrically programmable. One conventional approach to the implementation of an erase method for nonvolatile memory is disclosed, for example, in Japan Patent Publication Nos. 2000-348492 and H8-77782. The conventional approach variously describes a block erase mode, a multi block erase mode, and a chip erase mode.
An erase operation performed by a NOR flash memory is typically conducted on the basis of a defined “erase unit”, (i.e., a memory block size capable of being erased during a single erase operation). Emerging NOR flash memory devices are characterized by an increasing erase unit size. That is, where previous NOR flash memory had an erase unit of 0.5 M, emerging NOR flash memory has an erase unit of 2.0 M. This expansion of erase unit size follows an increase in the number of NOR flash memory devices incorporating multi level memory cells (MLCs). The incorporation of MLCs allows contemporary NOR flash memory to store more data per unit area of constituent chip size.
To accommodate an increasing erase unit size for NOR flash memory incorporating MLCs, the number of physical memory cells conditioned by an erase operation must be increased. For example, in order to realize an erase unit of 2.0 M in a NOR flash memory incorporating MLCs, the number of inner physical memory cells should be 1.0 M which is twice the conventional number of memory cells.
However, increasing the number of physical memory cells conditioned by an erase operation raises some difficult issues. Some of these issues will now be described using an assumption that the number of physical memory cells being conditioned in 1.0 M. First, because the number of physical memory cells is now double that of previous conventional NOR flash memory devices, the threshold voltage distribution (Vt distribution) for the 1.0 M memory cells may broaden following completion of an erase operation, as compared with the threshold voltage distribution for 0.5 M memory cells. FIG. 5 graphically illustrates this phenomenon. The results illustrated in FIG. 5 occur immediately after an erase operation is completed, but before “treatment” of the memory cells which is typical in erase operations for flash memory.
As is conventionally understood, it is necessary to prevent an over-erase condition for memory cells in NOR flash memory. Once the threshold voltage distribution has broadened, it is necessary to suppress the incidence rate of over-erase by raising the reference voltage used during erase verification. However, this means that the upper limit of the threshold voltage for an erased memory cell must be increased, thereby decreasing read margin for the memory cell.
Thus, in order to realize an erase threshold voltage distribution similar to that previously obtained for 0.5 M memory cells, an erase operation applied to 1.0 M memory cells must carefully consider the erase verification process and possibly adjustments to the memory cell fabrication process. Further, the prompt application of certain conventional suppression techniques becomes complicated.
It is further assumed, consistent with conventional practice, that the 1.0 M memory cells may be erased as two (2) 0.5 M memory cell units connected in series. In such a case, the use of conventional suppression techniques becomes possible with an erase threshold voltage distribution width typical for 0.5 M memory cells. Furthermore, since a conventionally similar erase operation may be used for each of the two 0.5 M memory cell units, potential alteration of the fabrication process is not required.
However, the serial erasure of two 0.5 M memory cell units unduly extends the time required to erase the entire 1.0 M memory cells using conventional techniques.